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Integrated Circuit Systems, Inc.
ICS95V847
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application: * Zero Delay Board Fan Out, SO-DIMM * Provides complete DDR registered DIMM solution with ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852 Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 5 differential clock distribution (SSTL_2) * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs Switching Characteristics: * CYCLE - CYCLE jitter: <60ps * OUTPUT - OUTPUT skew: <60ps * Period jitter: 30ps * DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
GND CLKC0 CLKT0 GND VDD CLK_INT CLK_INC AVDD AGND CLKC1 CLKT1 VDD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLKT4 CLKC4 CLKC3 CLKT3 VDD FB_INT FB_INC FB_OUTC FB_OUTT CLKT2 CLKC2 GND
24-Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
Functionality
INPUTS AVDD CLK_INT GND GND 2.5V (nom) 2.5V (nom) L H L H OUTPUTS PLL State CLK_INC CLKT CLKC FB_OUTT FB_OUTC H L H L L H L H H L H L L H L H H L H L Bypassed/off Bypassed/off on on
Block Diagram
FB_OUTT FB_OUTC
FB_INT FB_INC CLK_INC CLK_INT
ICS95V847
CLKT0 CLKC0
PLL
CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
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ICS95V847
Pin Descriptions
PIN NUMBER 5, 12, 20 1, 4, 13 8 9 3, 11, 15, 21, 24 2, 10, 14, 22, 23 6 7 16 PIN NAME VDD GND AVDD AGND CLKT[0:4] CLKC[0:4] CLK_INT CLK_INC FB_OUTT TYPE PWR PWR PWR PWR OUT OUT IN IN OUT Power supply, 2.5V Ground Analog power supply, 2.5V A n a l o g gr o u n d "Tr ue" Clock of differential pair outputs "Complementar y" clocks of differential pair outputs "True" reference clock input "Complementar y" reference clock input "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error DESCRIPTION
17 19 18
FB_OUTC FB_INT FB_INC
OUT IN IN
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels. ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog power input (AVDD). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT[4:0], CLKC[4:0]). ICS95V847 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. ICS95V847 is characterized for operation from 0C to 85C.
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ICS95V847
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND - 0.5V to VDD + 0.5V 0C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current High Impedance Output Current Input Clamp Voltage High-level output voltage Low-level output voltage SYMBOL I IH I IL IDD2.5 IDDPD IOZ VIK VOH VOL CONDITIONS VI = V DD or GND VI = VDD or GND CL = 0pf @ 200MHz CL = 0pf VDD = 2.7V, Vout = VDD or GND VDD = 2.3V Iin = -18mA IOH = -1 mA IOH = -12 mA IOL =1 mA IOH =12 mA VI = GND or V DD MIN 5 TYP MAX 5 148 100 10 -1.2 VDD - 0.1 1.7V 0.1 0.6 3.5 UNITS A A mA A mA V V V V V pF
CIN Input Capacitance1 1 Guaranteed by design at 233MHz, not 100% tested in production.
2.5
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ICS95V847
Recommended Operating Condition (see note1)
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature SYMBOL VDD, A VDD VIL VIH VIN VID V OX VIX IOH IOL TA 0 DC - CLKT, FB_INT AC - CLKT, FB_INT CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# MIN 2.3 -0.3 V DD/2 + 0.18 1.7 -0.3 0.36 0.7 VDD/2 - 0.15 VDD/2 - 0.2 V DD/2 TYP 2.5 0.4 2.1 VDD + 0.6 VDD + 0.3 VDD + 0.6 VDD + 0.6 V DD/2 + 0.15 V DD/2 + 0.2 -6.4 5.5 85 MAX 2.7 VDD/2 - 0.18 0.7 UNITS V V V V V V V V V V mA mA C
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing.
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ICS95V847
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 2.5V+0.2V @ 25oC 2.5V+0.2V @ 25oC 45 95 40 233 210 60 15 UNITS MHz MHz % s
Switching Characteristics (see note 3)
PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Phase error Output to Output Skew SYMBOL tPLH1 tPLL1 tEN tdis Tjit (per) t(jit_hper) t sl(i) t sl(o) Tcyc -Tcyc t(phase error) Tskew
4
CONDITION CLK_IN to any output CLK_IN to any output PD# to any output PD# to any output 100MHz to 200MHz 100MHz to 200MHz
MIN
TYP 5.5 5.5 5 5
MAX
UNITS ns ns ns ns ps ps V/ns V/ns ps ps ps
-30 -75 1 1 -50 0
100MHz to 200MHz
30 30 4 2.5 60 50 60
Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design.
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ICS95V847
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD/2 V(CLKC) ICS95V847 GND Figure 1. IBIS Model Output Load VDD/2 ICS95V847 Z = 60 C = 14 pF -VDD/2 R = 10 Z = 50 SCOPE
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FBOUTC YX, FBOUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS95V847
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX # YX
YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter
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ICS95V847
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t (hper_n) 1 fo t (hper_n+1)
t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter
80%
80% VID , VOD
Clock Inputs and Outputs
20% Rise tsl Fall tsl
20%
Figure 8. Input and Output Slew Rates
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ICS95V847
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 6.40 BASIC 0.252 BASIC E E1 4.30 4.50 .169 .177 0.65 BASIC 0.0256 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 24 D mm. MIN 7.70 MAX 7.90 MIN .303 D (inch) MAX .311
-Ce
b SEATING PLANE
aaa C
Reference Doc.: JEDEC Publication 95, MO-153 10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil)
Ordering Information
ICS95V847yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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